Figure 8.10

Another method to minimize sensitivity to overdrive is shown in Figure 8.1 l. The amplitude of the fundamental signal is first measured with the notch filter switched out. The harmonics are measured with the notch filter switched in. The insertion loss of the notch filter, XdB, must be added to the measured level of the harmonics.

OTCH FILTER REMOVES THE FUNDAMENTAL
SIGNAL TO MINIMIZE ANALYZER OVERDRIVE

Figure 8.11
MEASURING ADC DISTORTION USING FFTs

The speed of personal computers and the availability of suitable software now makes DSP bench testing of high speed ADCs relatively easy. A block diagram of a typical DSP PC-based test system is shown in Figure 8.12. In order to perform any DSP testing, the first requirement is a high speed buffer memory of sufficient width and depth. High speed logic analyzers make a convenient memory and eliminate the need for designing special hardware. The HP1663A is a 100MHz logic analyzer which has a simple IEEE-488 output port for easy interfacing to a personal computer. The analyzer can be configured as either a 16-bit wide by 8k deep, or a 32-bit wide by 4k deep memory. This is more than sufficient to test a high speed ADC at sample rates up to 100MHz. For higher sample rates, faster logic analyzers are available, but are fairly costly. An alternative to using a high speed logic analyzer is to operate the ADC at the desired sample rate, but only clock the final output register at an even sub-multiple of the sample clock frequency. This is sometimes called decimation and is useful for relaxing memory requirements. If an FFT is performed on the decimated output data, the fundamental input signal and its associated harmonics will be present, but translated in frequency. Simple algorithms can be used to find the locations of the signal and its harmonics provided the original signal frequency is known.

A SIMPLE PC-BASED TEST SYSTEM

Figure 8.12

FFT TESTING

Easy to use mathematical software packages, such as MathcadTM (available from MathSoft, Inc., 201 Broadway, Cambridge MA, 02139) are available to perform fast FFTs on most 486-based PCs. The use of a co~processor allows a 4096-point FFT to run in a few seconds on a 75MHz,486 PC. The entire system will run under the Windows environment and provide graphical displays of the FFT output spectrum. It can be programmed to perform SNR, S/(N+D), THD, IMD, and SFDR computations. A simple QuickBasic program transfers the data stored in the logic analyzer into a file in the PC via the IEEE-488 port (Reference 3, Section 16).

Properly understanding of FFT fundamentals is necessary in order to achieve meaningful results. The first step is to determine the number of samples, M, in the FFT record length. In order for the FFT to run properly, M must be a power of 2. The value of M determines the frequency bin width, Delta f = fs/M. The larger M, the more frequency resolution. Figure 8.13 shows the relationship between the average noise floor of the FFT with respect to the broadband quantization noise level. Each time M is doubled, the average noise in the Delta f bandwidth decreases by 3dB. Larger values of M also tend to give more repeatable results from run to run (see Figure 8.13).

RELATIONSHIP BETWEEN AVERAGE NOISE IN FFT BINS
AND BROADBAND RMS QUANTIZATION NOISE LEVEL


Figure 8.13

M values of 512 (for 8-bit ADCs), 2048 (for 10-bit ADCs), and 4096 (for 12-bit ADCs) have proven to give good accuracy and repeatability. For extremely wide dynamic range applications (such as spectral analysis) M=8192 may be desirable. It should be noted that averaging the results of several FFTs will tend to smooth out the noise floor, but will not change the average value of the floor.

In order to obtain spectrally pure results, the FFT data window must contain an exact integral number of sinewave cycles as shown in Figure 8.14. These frequency ratios must be precisely observed to prevent end-point discontinuity. In addition, it is desirable that the number of sinewave cycles contained within the data window be a prime number. This method of FFT testing is referred to as coherent testing because two locked frequency synthesizers are used to insure the proper ratio (coherence) between the sampling clock and the sinewave frequency. The requirements for coherent sampling are summarized in Figure 8.15.

Another method to minimize sensitivity to overdrive is shown in Figure 8.1 l. The amplitude of the fundamental signal is first measured with the notch filter switched out. The harmonics are measured with the notch filter switched in. The insertion loss of the notch filter, XdB, must be added to the measured level of the harmonics.

另一种将过载敏感性最小化的方法如图8.1 l所示。先旋进陷波滤波器测量基本信号的振幅。再旋进陷波滤波器测量谐波。陷波滤波器的介入损失，如多少分贝，需记入谐波测量值中。

OTCH FILTER REMOVES THE FUNDAMENTAL
SIGNAL TO MINIMIZE ANALYZER OVERDRIVE

陷波滤波器消除基波从而最小化分析仪过载

Figure 8.11
MEASURING ADC DISTORTION USING FFTs
用快速傅立叶变换算法测量模数转换器失真度

The speed of personal computers and the availability of suitable software now makes DSP bench testing of high speed ADCs relatively easy. A block diagram of a typical DSP PC-based test system is shown in Figure 8.12. In order to perform any DSP testing, the first requirement is a high speed buffer memory of sufficient width and depth. High speed logic analyzers make a convenient memory and eliminate the need for designing special hardware. The HP1663A is a 100MHz logic analyzer which has a simple IEEE-488 output port for easy interfacing to a personal computer. The analyzer can be configured as either a 16-bit wide by 8k deep, or a 32-bit wide by 4k deep memory. This is more than sufficient to test a high speed ADC at sample rates up to 100MHz.
如今个人计算机的速度及合适的应用软件使得 数字信号处理bench测试相对容易些。一种典型的电脑化数字信号处理测试系统的模块图如Figure 8.12所示。要实现任何数字信号处理测试，首先要有足够宽度和深度的高速缓存。高速逻辑分析仪对内存要求适中且免去了设计特殊硬件的烦恼。HP1663A是一种频率100Mhz的逻辑分析仪，它实现了一种简单的IEEE-488 输出端口，能很容易得连到PC上。这种仪器能将内存设置成16位宽度X8k的深度或32位的宽度X4k的深度。这样的设置对采样率为100MHz的高速模数转换测试完全足够。

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没翻完。翻不下去了，那么长